• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention relates to a data processing circuit of Plasma Display Panel-TeleVision (PDP-TV) which digitizes an analog video signal separated from a composite video signal and stores the bit by weight in a frame memory. The present invention consists of first to third A / D converters, first and second R, G and B PISOs, and a data recorder to convert analog video signals separated from NTSC composite video signals into digital video data. By storing the bit weights in the frame memory for each bit weight, the image data stored in the frame memory can be efficiently supplied to the address driver IC.
    公开号:KR20000021546A
    申请号:KR1019980040697
    申请日:1998-09-30
    公开日:2000-04-25
    发明作者:김세용
    申请人:전주범；대우전자 주식회사；
    IPC主号:
    专利说明:

    Data processing unit of a PDP television
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to PDP-TV (PDP-TV: Plasma Display Panel-TeleVision), and more particularly, to a data processing circuit of a PDP-TV which digitizes an analog video signal separated from a composite video signal and stores it by bit weight in a frame memory. will be.
    In general, a PDP is a flat panel display panel using a penning gas for discharge, i.e., gases based on Ne or Helium gas having a relatively high atmospheric pressure (over 100 Torr) are coated with a dielectric. The panel which uses the light emission phenomenon obtained by discharging between narrow electrodes.
    The penning gas is mainly Ne + Xe, Ne + He + Xe, and the reason for using such a mixed gas is that the discharge start voltage can be lowered when the mixed gas is more than one gas component. The discharge start voltage depends on the type of gas, the fanning gas pressure, and the structure and shape of the panel.
    The PDP has the following advantages over other display devices.
    First of all, the PDP is not limited to the number of horizontal and vertical display lines, so that a large size can be manufactured and multiplexing techniques can be used to reduce the number of driving circuits.
    Since the discharging material is a gas, the refractive index value is 1, which means that the light is not extinguished by the internal reflection and the external light is not reflected or scattered by the display material. In addition, unlike other flat panels, the PDP is sealed with glass above 400 ° C, which means that the PDP can operate even under high humidity conditions or the presence of reactive gases. It is only a change.
    The PDPs are classified into AC type PDPs and DC type PDPs according to the type of driving voltage applied to the discharge cells. The AC type PDP is driven by a sine wave AC voltage or a pulse voltage, while the DC type PDP is driven by a DC voltage. In addition, in the AC type PDP, the electrode is covered with a dielectric of glass, whereas in the DC type PDP, the electrode is exposed as it is and a discharge current flows while the discharge voltage is applied.
    In general, PDP-TV cannot display interlaced analog NTSC composite video signal as it is because of the characteristics of PDP and converts interlaced analog NTSC composite video signal into sequential scanning digital video data. TV images can be displayed.
    In addition, the PDP-TV divides and drives one field screen into a plurality of subfield screens to realize gray scale of an image. To this end, the PDP-TV drives one frame of image data with the most significant bit (MSB). : Since most significant bit (LSB) to least significant bit (LSB) needs to be rearranged, an area capable of storing one frame of image data, that is, a frame memory is provided.
    As described above, one frame of R (Red), G (Green), and B (Blue) data should be stored for each bit weight. PDP-TV is an analog R, G, The B signal must be converted into digital R, G, and B data and stored in the frame memory for each bit weight. In the related art, a specific circuit for performing such data processing is not implemented so that an NTSC composite video signal can be accurately displayed on a PDP. There was no problem.
    The present invention has been made to solve the above problems, the data processing circuit of the PDP-TV to convert the analog video signal separated from the NTSC composite video signal to digital video data and then classified by bit weight and stored in the frame memory The purpose is to provide.
    In order to achieve the above object, the data processing circuit of the PDP-TV according to the present invention includes an audio / video unit for separating analog R, G, and B signals from a composite video signal, and digital R, G, and B data in one frame. A PDP-TV having a memory unit for storing a quantity, the first A / D (Analog / Digital) converter for digitizing and outputting the analog R signal, and the second A / D for digitizing and outputting the analog G signal. A third A / D converter that digitizes and outputs the analog B signal, and a second repeating load and shift operation so that the R data output from the first A / D converter is classified according to bit weights. First and second G PISs alternately repeating the load operation and the shift operation so that the first and second R PISOs (PISO) and the G data output from the second A / D converter are classified by bit weights. O and first and second B PISOs alternately repeating the load operation and the shift operation so that the B data output from the third A / D converter is classified by bit weight, and the first or second R, G, And a data recording unit which records R, G, and B data shifted from B PISO and output for each bit weight in order in the memory unit.
    1 is a schematic configuration diagram of a PD TV to which the present invention is applied;
    FIG. 2 is a schematic configuration diagram of the data processor of FIG. 1.
    <Description of the symbols for the main parts of the drawings>
    110: audio / video section 120: data processing section
    120-1 to 120-3: A / D converter 120-4 to 120-9: PISO
    120-10: data recording section 130: memory section
    Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    1 is a schematic configuration diagram of a PDP-TV to which the present invention is applied, and the audio / video unit 110 receives an NTSC composite video signal through an antenna and outputs analog R (Red), G (Green), and B (Blue). The signal is separated from the horizontal and vertical sync signals (Hsync, Vsync), an average picture level (APL) corresponding to the average value of the luminance signal is obtained, and provided to the data processor 120. Here, the NTSC composite video signal has an interlaced scanning method in which one frame consists of two odd and even fields, the horizontal sync signal Hsync has a frequency of about 15.73KHz and the vertical sync signal Vsync has a frequency of about 60Hz. .
    The data processor 120 converts the analog R, G, and B signals received from the audio / video unit 110 into N-bit digital image data, respectively, and then converts the R, G, and B data from the most significant bit (MSB) to the least significant bit. The data is rearranged by the bit weights up to the LSB and stored in the memory unit 140. In this case, when the analog image signal is converted into N-bit digital image data, 2N gray scale is implemented. For example, when converting an analog video signal into 8-bit digital video data, 2 8 = 256 gray levels are implemented.
    Although not shown in the drawing, the memory unit 130 includes first and second frame memories that store R, G, and B data, respectively, by one frame. For example, when 2 8 = 256 gray scales are implemented in a PDP having a resolution of 853 × 480, the first or second frame memory has one frame, that is, 853 × 3 (R, G, B) × 480 × 8 bits = about It should be able to store 10Mbit of image data. Here, the two frame memories are provided so that the recording and reading of the image data by the data processing unit 120 and the data interface unit 140 are simultaneously performed. That is, while one of the two frame memories is operated in the image data recording mode, the other is operated in the image data reading mode.
    The data interface 140 shown in FIG. 1 stores image data read from the first or second frame memory by one line, and then the upper and lower address driving integrated circuit (IC) units 150-1 and 150-. The data is read in the form of data required by 2) and supplied to the upper and lower address driver IC units 150-1 and 150-2.
    The upper address driving IC unit 150-1 addresses the odd-numbered address electrode lines of the PDP 200 according to the “high” and “low” of R, G, and B data supplied from the data interface unit 140. The lower address driving IC unit 150-2 applies a pulse and the even-numbered address electrode of the PDP 200 according to the "high" and "low" of the R, G, and B data supplied from the data interface unit 140. Apply address pulses to each line
    The scan and sustain driving IC unit 160 shown in FIG. 1 applies scan pulses and sustain pulses to the scan and sustain electrode lines of the PDP 200, respectively, and the timing controller 170 controls the audio / video unit 110. Receives the horizontal and vertical synchronization signals Hsync and Vsync output to generate a data read clock (data read CLK) and supply them to the data processor 130, and generate various logic control pulses to supply the high voltage driving circuit unit 180. do.
    The high voltage driving circuit unit 180 combines the DC voltages supplied from the AC-DC converter 190 according to various logic control pulses output from the timing controller 170 to upper and lower address driving IC units 150-1. 150-2) and the high voltage control pulse required by the scan and sustain driver IC unit 160 to drive the PDP 200. In addition, the data streams supplied by the data interface unit 140 to the upper and lower address driver IC units 150-1 and 150-2 are also raised to an appropriate voltage level to enable selective writing to the PDP 200.
    The AC-DC converter 190 generates AC voltages (220V AC, 60Hz) as inputs to generate high voltages required to combine the electrode driving pulses and all DC voltages required by each component constituting the system. Supply.
    2 is a schematic configuration diagram of the data processor illustrated in FIG. 1, wherein the data processor 120 includes a first A / D converter 120-1, a second A / D converter 120-2, and Third A / D converter 120-3, first R PISO 120-4, second R PISO 120-5, first G PISO 120-6, and second G PISO And a first B PISO 120-8, a second B PISO 120-9, and a data recording unit 120-10.
    The first A / D converter 120-1 digitizes the analog R signal separated by the audio / video unit 110 shown in FIG. 1 to digitize the first or second R PISOs 120-4 and 120-5. Will output
    The second A / D converter 120-2 digitizes the analog G signal separated by the audio / video unit 110 shown in FIG. 1 to form the first or second G PISOs 120-6 and 120-7. Will output
    The third A / D converter 120-3 digitizes the analog B signal separated by the audio / video unit 110 shown in FIG. 1 to form the first or second B PISOs 120-8 and 120-9. Will output
    The first and second R PISOs 120-4 and 120-5 alternately repeat the load operation and the shift operation so that the R data output from the first A / D converter 120-1 is classified by bit weights. .
    The first and second G PISOs 120-6 and 120-7 alternately repeat the load operation and the shift operation so that the G data output from the second A / D converter 120-2 is classified by bit weights. .
    The first and second B PISOs 120-8 and 120-9 alternately repeat the load operation and the shift operation so that the B data output from the third A / D converter 120-3 is classified by bit weight. .
    In the above, two R, G, and B PISOs 120-4 to 120-9 are provided. Each of the R, G, and B PISOs 120-4 to 120-9 is outputted by shifting previously loaded image data by bit weight while one of them loads image data. That is, to perform the load operation and the shift operation of the image data at the same time.
    The data recording unit 120-10 shown in FIG. 2 sequentially shifts R, G, and B data output by bit weights shifted from the first or second R, G, and B PISOs 120-4 through 120-9. Writing to one of the two frame memories of the memory unit 130 shown in FIG.
    Referring to the operation of the data processing unit 120 configured as described above in more detail as follows.
    In the following description, an example of implementing 2 8 = 256 gray scales in the PDP 200 having a resolution of 853 × 480 will be described as an example.
    First, when the resolution of the PDP 200 is 853 × 480 and 256 gray levels are implemented, the first A / D converter 120-1 converts the analog R signal separated from the audio / video unit 110 into 8-bit R data. The second A / D converter 120-2 converts the analog G signal separated by the audio / video unit 110 into 8-bit G data and converts the first R PISO 120-4. The third A / D converter 120-3 converts the analog B signal separated from the audio / video unit 110 into 8-bit B data and outputs the first B PISO 120 to the G PISO 120-6. -8) The operations of the first to third A / D converters 120-1 to 120-3 are simultaneously performed.
    The first R PISOs 120-4 and 120-5 load R data input in parallel by 8 bits from the first A / D converter 120-1 in 16 times for a total of 8 × 16 = 128 bits. The first G PISOs 120-6 and 120-7 are output to the data recording unit 120-10 while sequentially shifting eight times from the most significant bit MSB to the least significant bit LSB eight times. 2 Loads 128 bits of G data input in parallel by 8 bits from the A / D converter 120-2 in total 16 times, and then performs 8 times of 16 bits from the most significant bit (MSB) to the least significant bit (LSB). R data outputted to the data recording unit 120-10 while sequentially shifting, and the first B PISOs 120-8 and 120-9 are input in parallel by 8 bits from the third A / D converter 120-3. After a total of 128 bits are loaded 16 times, the data is outputted to the data recording unit 120-10 while sequentially shifting 8 times from the most significant bit (MSB) to the least significant bit (LSB). Here, the operations of the first R, G, and B PISOs 120-4, 120-6, and 120-8 are simultaneously performed.
    In the above, while the first R, G, and B PISOs 120-4, 120-6, and 120-8 respectively load and shift the 128-bit image data, the second R, G, and B PISOs 120-5, 120 are used. The data recording unit 120-10 shifts the previously loaded 128-bit image data, as opposed to the first R, G, and B PISOs 120-4, 120-6, and 120-8, respectively. ) And then 128 bits of new image data output from the first to third A / D converters 120-1 to 120-3.
    On the other hand, the data recording unit 120-10 is output in parallel by 16x3 (R, G, B) = 48 bits in the first or second R, G, B PISO (120-4 to 120-9) R, G, and B data are written in order to one of the two frame memories of the memory unit 130. In addition, the image data recording operation is repeated until one frame of image data is recorded in the frame memory.
    As a result, one frame of R, G, and B data is stored for each bit weight in the frame memory.
    As described above, the present invention has an effect of digitizing an analog video signal separated from the NTSC composite video signal and storing the same in the frame memory for each bit weight so that the image data stored in the frame memory can be efficiently supplied to the address driver IC. .
    权利要求:
    Claims (1)
    [1" claim-type="Currently amended] In a PDP-TV having an audio / video section for separating analog R, G, and B signals from a composite video signal, and a memory section for storing digital R, G, and B data by one frame,
    A first A / D converter for digitizing and outputting the analog R signal;
    A second A / D converter for digitizing and outputting the analog G signal;
    A third A / D converter for digitizing and outputting the analog B signal;
    First and second R PISOs alternately repeating a load operation and a shift operation so that the R data output from the first A / D converter is classified by bit weight;
    First and second G PISOs alternately repeating a load operation and a shift operation such that the G data output from the second A / D converter is classified by bit weights;
    First and second B PISOs alternately repeating a load operation and a shift operation so that B data output from the third A / D converter is classified by bit weights;
    And a data recorder configured to sequentially write the R, G, and B data shifted from the first or second R, G, and B PISOs and output according to bit weights, in the memory unit. .
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    同族专利:
    公开号 | 公开日
    KR100403515B1|2003-12-18|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-09-30|Application filed by 전주범, 대우전자 주식회사
    1998-09-30|Priority to KR10-1998-0040697A
    2000-04-25|Publication of KR20000021546A
    2003-12-18|Application granted
    2003-12-18|Publication of KR100403515B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-1998-0040697A|KR100403515B1|1998-09-30|1998-09-30|PDTV's data processing circuit|
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